10. CACHE Instructions

10.13 Hit Invalidate (S)

1. The processor reads the Tags from both ways of the secondary cache at the address pointed to by the PA of the CACHE instruction. If the tag entry's STag matches the CACHE instruction PA, and the State of the entry is not equal to 00 (Invalid), then a Hit has occurred in that entry. If there is no Hit, the CACHE instruction completes.

2. The processor checks each entry in the primary caches to determine which corresponds to the CACHE instruction PA and the PIdx read from the secondary cache tag array. Any entry which matches is invalidated. No write back is required by Hit Invalidate (S).

3. The processor sets the tag array entry of the secondary cache block which was hit to State = 00 (Invalid), Tag = PA of CACHE instruction, and PIdx = VA[13:12] of CACHE instruction.

4. ECC is generated.

5. The MRU bit is written to point to the way opposite to that being invalidated.

6. If the processor Eliminate Request mode bit, PrcElmReq, is set, a processor eliminate request is sent to notify the external agent that a block in the secondary cache has been invalidated.

7. Hit Invalidate (S) sets the CH bit if it hits in the secondary cache.

8. Once the CH bit is set it stays set until cleared by a MTC0 instruction, or the next CacheOp that can change the CH bit.

Hit CacheOps can cause cache error exceptions if they check ECC or parity bits.